A signal line driving circuit of the present invention is applicable to a variety of systems. The following will describe the case where the signal line driving circuit is applied to an image display device, and in particular to an active-matrix type liquid crystal display device. However, the signal line driving circuit according to the present invention is not just limited to this, and evidently, it is equally effective in the other image display devices or systems, wherein the present invention is applicable.
As a kind of conventional image display devices, liquid crystal display devices of an active-matrix driving system are known. As shown in FIG. 10, the liquid crystal display device includes a pixel array 1, a scanning signal line driving circuit 2 and a data signal line driving circuit 3. The pixel array 1 includes scanning signal lines GL (GLj, GLj+1) and data signal lines SL (SLi, SLi+1) crossing one another, and pixel (PIX, as illustrated in FIG. 10) 4 which is arranged in matrix. The pixel 4 is formed within each area enclosed by two adjacent scanning signal lines GL and two adjacent data signal lines SL.
The data signal line driving circuit 3 makes sampling of a received video signal DAT (data) in synchronism with a timing signal such as a clock signal CKS, and amplifies it as required, and outputs it into each data signal line SL. The scanning signal line driving circuit 2 successively selects the scanning signal line GL in synchronism with a timing signal such as a clock signal CKG, and by controlling opening and closing of a switching element (described later) within pixel 4, applies the video signal DAT which was outputted to each data signal line SL to each pixel 4, and stores the video signal DAT on each pixel 4.
The pixel 4, as shown in FIG. 11, is composed of a pixel transistor SW (electric field effect transistor) as the switching element, and a pixel capacitance CP including a liquid crystal capacitance CL (auxiliary capacitance CS is added as required). In the pixel 4 having this arrangement, the data signal line SL is connected to one of the electrodes of the pixel capacitance CP via a drain and source of the pixel transistor SW, the gate of the pixel transistor SW is connected to the scanning signal line GL, and the other electrode of the pixel capacitance CP is connected to a common electrode line which is common to all pixels (not shown). With this arrangement, when a voltage is applied to the liquid crystal capacitance CL of the pixel capacitance CP, the transmittance or reflectance of the liquid crystal is modulated, and a picture in accordance with the video signal DAT is displayed on the pixel array 1.
The following will explain how the video signal DAT is outputted into the data signal line SL by the data signal line driving circuit 3. Although driving modes for the data signal line SL include a point-sequential driving mode and a line-sequential driving mode, merely the latter will be discussed below.
The scanning signal line driving circuit 2 is, as illustrated in FIG. 12 for example, provided with a shift register 101 which transfers start pulses SPG successively at the timing of the clock signal CKG. In this scanning signal line driving circuit 2, a shift pulse GNn (n=1, 2), which is an AND of output signals of two adjacent shift circuits 101a, are outputted from an AND gate 101b, and the shift pulse GNn thus outputted and a width specifying pulse GPS, which is externally inputted so as to specify the pulse length of the shift pulse GNn, are subjected to logical AND by an AND gate 103, and a pulse of the logical AND thus obtained is outputted to a scanning signal line GLn via a buffer circuit 104.
In the foregoing scanning signal line driving circuit 2, the AND gate 103 that outputs the AND of the shift pulse GNn and the width specifying pulse GPS, as shown in FIG. 13, is realized by a common CMOS AND circuit (CMOS OR circuit when the input signal is a negative logic). This CMOS AND circuit is composed of two p-channel transistors 111 and 112 which are connected in parallel, and two n-channel transistors 113 and 114 serially connected to the p-channel transistors 111 and 112. The gates of the p-channel transistor 111 and the n-channel transistor 113 receive an input signal IN1, and the gates of the p-channel transistor 112 and the n-channel transistor 114 receive an input signal IN2. The amplitudes of these input signals IN1 and IN2 are equal to that of a power voltage VDD.
Further, in recent years, a technique which forms the scanning signal line driving circuit 2 and the data signal line driving circuit 3 on a substrate 5 integrally with the pixel array 1 has been focussed, so as to achieve miniatualization of image display devices, enhance reliability, reduce costs, etc. In such driving circuits integrated with the pixel array 1, as with the latest ICs, techniques for attaining lower input voltages (smaller amplitudes), aiming at reduction of power consumption and achievement of high-speed performance and the like, have been developed. However, in a driving circuit, the use of a voltage higher than an input voltage is required so as to obtain a predetermined driving power. Accordingly, as shown in FIG. 14, the scanning signal line driving circuit 2 includes a level shifter (LS, as illustrated in Figures) 105 which raises the width specifying pulse GPS of a small amplitude.
In recent years, to achieve lower power consumption of liquid crystal display devices, and higher operation speed and the like, demands have increased as to the lower load of internal wiring (reduction of parasitic capacitance) and the miniatualization of driving circuits so as to reduce a periphery portion (edge portion) where the driving circuits are to be provided, i.e. to reduce the number of elements composing the driving circuits. Accordingly, in the foregoing scanning signal line driving circuit 2, it is required to realize a circuit structure which is capable of a higher-speed operation, which has the less parasitic capacitance, and which has a smaller number of elements, in comparison with the CMOS AND circuit forming the AND gate 103.
However, in the scanning signal line driving circuit 2, because the level shifter 105 is provided at the input section of the signal line which transmits the width specifying pulse GPS, the GPS whose amplitude has been increased by the level shifter 105 is supplied to each AND gate 103 via signal lines. This is one of the factors that causes the increase in power consumption in the signal line driving circuits.